Revolutionizing Network Security with Anomaly Detection
Discover how NEUROPULS is transforming network security with real-time threat detection—read the full article now!View more
NEUROPULS First General Assembly in Lisbon
The inaugural session of the NEUROPULS Project General Assembly, hosted by Luis Miguel Silveira and team at the Institute of Systems and Computer Engineering, Research and Development, took place in Lisbon on September 4-5, 2023. The assembly brought together 27 members from prestigious institutions.View more
NEUROPULS General Assembly #4: Progress in Canazei
From December 9–10, 2024, the NEUROPULS consortium convened for its 4th General Assembly in the serene setting of Canazei, Italy. Hosted by the University of Verona, this two-day event was a milestone in the project’s journey, combining rigorous technical discussions with moments of team-building in the breathtaking Dolomites.View more
European Neuromorphic Computing Perspectives #1 : NimbleAI
Europe’s neuromorphic computing landscape is rich, diverse, and full of inspiring initiatives. To better reflect this collective momentum and to encourage stronger connections between projects, we are launching a new interview series called “European Neuromorphic Computing Perspectives.”View more
Abstract
The Future of Computing: Unlocking the Potential of Neuromorphic Technology for Low-Power and Secure Edge Computing. With the rise of self-driving vehicles, IoT, and Industry 4.0, the need for processing massive amounts of data locally and securely has never been greater. Traditional electronic computing systems have limitations such as high latency and low energy-efficiency, which are no longer suitable for these applications. Neuromorphic computing, a brain-inspired approach, is the solution to these problems.
However, current neuromorphic electrical computing systems have their own limitations, which is why the NEUROPULS project is developing next-generation low-power and secure edge-computing systems. By utilizing novel photonic computing architectures and security layers based on photonic PUFs, augmented silicon photonics CMOS-compatible platforms, and emerging non-volatile phase change materials, this project aims to demonstrate a two-order of magnitude improvement in energy efficiency. With RISC-V compliant interfaces and a novel full-system simulation platform, NEUROPULS will revolutionize the future of computing.
Objectives
NEUROPULS will develop -for the first time- secure hardware accelerators based on novel neuromorphic architectures and PUF-based security layers leveraging the benefits offered by the integration of photonics, PCMs and III-V materials. This integration will provide superior security, energy-efficiency, and speeds for spiking and formal recurrent NNs when compared to current available technology for the selected use-cases.
- Objective 1: Development of a CMOS-compatible platform addressing the integration of silicon photonics with PCMs and III-V materials
- Objective 2: Development of a low-power and secure RISC-V interfaced neuromorphic accelerator based on the integration of silicon photonics, novel PCMs, and Q-switched III-V lasers
- Objective 3: Development of a system-level simulation platform for PCM-based photonic low-power accelerators using photonic security layers
This project has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No 101070238 . This publication [communication] reflects the views only of the author, and the Commission cannot be held responsible for any use which may be made of the information contained therein.
Centre National de la Recherche Scientifique
[ CNRS ]
France
Fabio Pavanello
Fabio Pavanello
Photonics for hardware security, neuromorphic computing, and communications - Project Coordinator, development of PUFs and PCM devices
ECOLE CENTRALE DE LYON
[ ECL ]
France
Cédric Marchand
Cédric Marchand
Emerging technologies for hardware security of computing architectures.
UNIVERSITE DIJON BOURGOGNE
[ UB ]
France
Benoit Cluzel
Benoit Cluzel
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
[ CEA LETI ]
France
Benoit Charbonnier
Benoit Charbonnier
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UNIVERSITEIT GENT
[ UGent ]
Belgium
Peter Bienstman
Peter Bienstman
Professor at University of Gent
POLITECNICO DI TORINO
[ POLITO ]
Italy
Alessandro Savino
Alessandro Savino
POLITO PI and WP6 leader
INSTITUTO DE ENGENHARIA DE SISTEMAS E COMPUTADORES, INVESTIGACAO E DESENVOLVIMENTO EM LISBOA
[ INESC ID ]
Portugal
L. Miguel Silveira
L. Miguel Silveira
INESC-ID Project Coordinator, work in Modeling and Simulation
BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
[ BSC CNS ]
Spain
Francisco Cazorla
Francisco Cazorla
Hardware for high-performance systems and edge systems
HEWLETT PACKARD ENTERPRISE BELGIUM
[ HPE Belgium ]
Belgium
Thomas Van Vaerenbergh
Thomas Van Vaerenbergh
WP7 - Dissemination and exploitation - leader
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ALBORA TECHNOLOGIES SL
[ AT ]
Spain
Anselm Adams
Anselm Adams
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ETHNIKO KAI KAPODISTRIAKO PANEPISTIMIO ATHINON
[ NKUA ]
Greece
Dimitris Gizopoulos
Dimitris Gizopoulos
National and Kapodistrian University of Athens PI
LUDWIG-MAXIMILIANS-UNIVERSITAET MUENCHEN
[ LMU MUENCHEN ]
Germany
Jonas Tillinger
Jonas Tillinger
ARGOTECH AS
[ ARGO ]
Czech Republic
František Kaván
František Kaván
Complete packaging services for Neuropuls photonic and electronic structures. Designs, simulations, prototyping.
UNIVERSITA DEGLI STUDI DI VERONA
[ UNIVR ]
Italy
Mariano Ceccato
Mariano Ceccato
Associate professor in Computer Science at Univ. of Verona
TECHNISCHE UNIVERSITAT BERLIN
[ TUB ]
Allemagne
Jean-Pierre Seifert
Jean-Pierre Seifert
Professor for Computer & Communication Security, TU Berlin, Germany
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news
New article on Open Access Gouvernement: Security Layers for Neuromorphic Photonic Accelerators
2025-07-02
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Neuropuls & Hewlett Packard Enterprise at the 10th edition of the PIC Magazine & PIC International Conference
2025-05-10
Workshop on Advancing Neuromorphic Technology Research and Commercialization in Kioto, Japan
2025-05-05
NEUROPULS project at the XIII Optoelectronics and Photonics Winter School (AIT2025)
2025-02-27
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events
Project General Assembly #4
NEUROPULS fourth Project General Assembly has been held on October 2nd and 3rd in Bruxelles, Belgium. The assembly has been hosted by HPE Belgium, two of the project's partners to discuss the progress of the project and plan for future activities.
PROJECT PROGRESS MEETING #7
The seventh Project Progress Meeting will take place via videoconference on Friday, 4th of August from 3:00 P.M. to 4:00 P.M. to assess project overall progress, discuss objectives, workplan, next face-to-face meeting, communication.
PROJECT PROGRESS MEETING #6
The sixth Project Progress Meeting will take place via videoconference on Friday, 4th of April from 3:00 P.M. to 4:00 P.M. to assess project overall progress, discuss objectives, workplan, next face-to-face meeting, communication.
PROJECT GENERAL ASSEMBLY #3
NEUROPULS third Project General Assembly will be held on December 9 and 10 in Canazei, Italy. The assembly will be hosted by University of Verona (UNIVR), one of the project's partners to discuss the progress of the project and plan for future activities.
PROJECT PROGRESS MEETING #5
The fifth Project Progress Meeting will take place via videoconference on Friday, 4th of October from 3:00 P.M. to 4:00 P.M. to assess project overall progress, to discuss objectives, workplan, next face-to-face meeting, communication.
PROJECT PROGRESS MEETING #4
The fourth Project Progress Meeting will take place via videoconference on Friday, 5th of July from 3:00 P.M. to 4:00 P.M. to assess project overall progress, to discuss objectives, workplan, next face-to-face meeting, communication.
PROJECT GENERAL ASSEMBLY #2
The second project general assembly of NEUROPULS will be held on March the 21st and 22nd in Barcelona, Spain. The assembly will be hosted by BSC (Barcelona Supercomputing Center), one of the project's partners to discuss the progress of the project and plan for future activities.
PROJECT PROGRESS MEETING #3
The third Project Progress Meeting will take place via videoconference on Friday, 1st of December from 3:00 P.M. to 4:00 P.M. to assess project overall progress, to discuss objectives, workplan, next face-to-face meeting, communication.
Project General Assembly #1
NEUROPULS has announced that its first project general assembly will be held on September 4 and 5 in Lisbon, Portugal. The assembly will be hosted by INESC-ID, one of the project's partners to discuss the progress of the project and plan for future activities.
PROJECT PROGRESS MEETING #2
The second Project Progress Meeting will take place via videoconference on Thursday, 6th of April from 3:00 P.M. to 4:00 P.M. to assess project overall progress, to discuss objectives, workplan, next face-to-face meeting, communication.
Project Progress Meeting #1
The first Project Progress Meeting will occur via videoconference on Thursday, 6th of April from 3:00 P.M. to 4:00 P.M. to assess project overall progress, to discuss objectives, workplan, next face-to-face meeting, communication.
NEUROPULS Kick-Off Meeting - 2023
The Kick-Off Meeting of NEUROPULS project will take place in Ecully (FR) on the 26th of January, 2023
publications
Publications in conference proceedings/Workshops
- D. Corradini, M. Pasqua, M. Ceccato, "Automated Black-box Testing of Mass Assignment Vulnerabilities in RESTful APIs", 2023 IEEE/ACM 45th International Conference on Software Engineering (ICSE), Melbourne, Australia, 2023
- F. Pavanello et al., "NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS", 2023 IEEE European Test Symposium (ETS), Venezia, Italy, 2023
- N. Marastoni, M. Ceccato, "Remote Attestation of IoT Devices using Physically Unclonable Functions: Recent Advancements and Open Research Challenges", 5th Workshop on CPS&IoT Security and Privacy (CPSIoTSec '23). Association for Computing Machinery, New York, NY, USA
- F. Pavanello et al., "Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies", 2023 IEEE 41st VLSI Test Symposium (VTS), San Diego, CA, USA, 2023
- O. Chatzopoulos et al., "Enabling Design Space Exploration of RISC-V Accelerator-rich Computing Systems on gem5", RISC-V Summit 2023, Barcelona, Spain, 2023
- O. Chatzopoulos et al., "Energy Efficiency of Out-of-Order CPUs: Comparative Study and Microarchitectural Hotspot Characterization of RISC-V Designs", 2023 IEEE International Symposium on Workload Characterization (IISWC), Ghent, Belgium, 2023
- D. Gizopoulos, G. Papadimitriou, O. Chatzopoulos, "Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures", 2023 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2023
- D. Agiakatsikas et al., "Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs", IEEE/ACM International Symposium on Microarchitecture (MICRO), Toronto, ON, Canada, 2023
- F. Pavanello et al., "Security layers and related services within the Horizon Europe NEUROPULS project", 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024
- A.Lugnan et al., "On-chip photonic neural network for multi-wavelength time-dependent signal processing", 2024 IEEE Photonics Conference (IPC), Rome, Italy, 2024
- A.Lugnan et al., "Large-scale neural network in passive silicon photonics for biologically plausible learning", 2024 SPIE Conference, Volume 13017, 2024
- A.Carpegna, A. Savino, S. Di Carlo, "Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge" IEEE Transactions on Emerging Topics in Computing, 2168-6750, 2024
- Carpegna et al., “Neuromorphic Heart Rate Monitors: Neural State Machines for Monotonic Change Detection”, 2024 IEEE Biomedical Circuits and Systems Conference (BioCAS), Xi'an, China, 2024
- O. Chatzopoulos et al., "SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs", 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Indianapolis, IN, USA, 2024
- N. Karystinos et al., "Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation", 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, 2024
- D. Gizopoulos et al., "Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale Measurements", 2024 IEEE European Test Symposium (ETS), The Hague, Netherlands, 2024
- M. Hejda et al., "Neuromorphic architectures based on augmented silicon photonics platforms", 2024 DAC, num. 359, 2024
- O. Chatzopoulos et al., "gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures", 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, United Kingdom, 2024
- S. Adit et al., "Silent Data Errors: Sources, Detection, and Modeling", 2023 IEEE 41st VLSI Test Symposium (VTS), San Diego, CA, USA, 2023
- D. Gizopoulos et al., "Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures", 2023 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2023
- N. Karystinos et al., "Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation", 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, 2024
- A. Foradori et al., " Leveraging nonlinear dynamics in silicon microring resonator arrays for image classification via reservoir computing", Proceedings of the SPIE, AI and Optical Data Sciences VI, Volume 13375, 2025
- A. Carpegna et al, "Neuromorphic Heart Rate Monitors: Neural State Machines for Monotonic Change Detection", Proceeding of the IEEE Biomedical Circuits (BioCAS), 2024
Publications in Journals
- G. Papadimitriou et al., "Silent Data Corruptions: Microarchitectural Perspectives", IEEE Transactions on Computers, vol. 72, no. 11, 2023
- A.Lugnan et al., “Emergent self-adaptation in an integrated photonic neural network for backpropagation-free learning”, Research Gate, 2023
- P. Noé et al., “Phase‐Change and Ovonic Materials (Fourth Edition)”, IPSS, vol. 17, issue 8, 2023
- A.Albanese et al., "Optical Properties of GeSe1-x Tex Chalcogenide Materials Promising for on-Chip Low and Ultra-Low Loss Reconfigurable Photonics and Nonlinear Devices", IPSS, vol. 18, Issue 10, 2024
- F. Pavanello, B. Charbonnier, P. Noé, "Phase-change materials for photonic applications", Photonique, num. 125, 2024
- M. Yan et al., "Emerging opportunities and challenges for the future of reservoir computing", Nature Communications, vol. 15, num. 2056, 2024
- M. Gomes de Queiroz et al., "The Impact of Feature Representation on the Accuracy of Photonic Neural Networks", APL Machine Learning, vol. 2, 2024
- F. Marchesin et al., "Braided interferometer mesh for robust photonic matrix-vector multiplications with non-ideal components", Optic Express, vol. 33, num. 2 , 2025
- A. Lugnan et al., "Reservoir computing with all-optical non-fading memory in a self-pulsing microresonator network", Advanced Optical Materials, 2025
- A. Albanese et al., "Nitrogen-Doped GeSe1−xTex Chalcogenide Thin Films: A Candidate for On-Chip Low-Loss Reconfigurable Photonics and Nonlinear Device Applications", Research Gate, 2025
- R. Dwivedi, F. Pavanello, R. Orobtchouk, "An Ultra-low-loss Compact Phase-Change Material-based Hybrid-mode Interferometer for Photonic Memories", APL Materials, Volume 13, Issue 4, 2025
- R. Sawant et al., "High-Endurance and Energy-Efficient All-Optical Programming of Scalable Silicon Waveguides with Integrated Phase-Change Material Patches", Advanced Optical Materials, July 2025
Preprints
- G. Fragkoulis et al., “Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension”, arXiv:2411.12444, 2024
- P. Jimenez et al., “Complexity Assessment of Analog Security Primitives Using the Disentropy of Autocorrelation”, arXiv:2402.17488, 2025
- M. Gomes de Queiroz et al., "Unfair Photonics? How Encoding May Lead to Bias in Photonic Neural Networks", 2025
- D. Brunner et al., "Roadmap on Neuromorphic Photonics", arXiv:2501.0791, 2025
Publications for the broad public
- F. Pavanello, "Lighting the way to better security - The NEUROPULS photonics-based approach", HIPEAC info, vol. 72, 2024
- F. Pavanello, "A novel route to secure and low-power accelerators for edge computing", Open Access Government, 2024
- G. Papadimitriou, D. Gizopoulos, "Accelerating the development of secure and reliable photonic and electronic systems", Open Access Government, 2025
- B. Charbonnier et al., "Phase change materials for reconfigurable photonic integrated circuits", Open Access Government, 2025
- F. Pavanello, "Security layers for neuromorphic photonic accelerators", Open Access Government, July 2025
- F. Pavanello, M. Hejda, "Brain-like chips are boosting computers and battling cybercrime", Horizon Magazine, June 2025
Use-cases
- M. Hejda et al., "Use case n.1: Revolutionizing Network Security: How NEUROPULS is Leading the Way with Advanced Anomaly Detection", 2024
- A. Gusi et al., "Use case n.2: Protecting Critical Applications: The Role of GNSS Anti-Jamming in the NEUROPULS Project", 2024
- R. Pujol et al., "Use case n.3: Driving into the Future: NEUROPULS and the Next Generation of Autonomous Vehicle Performance Efficiency", 2024
documents
D1.2 Data Management Plan
D5.1 Accelerators models and components: iteration 1
D5.3 Memory hierarchy models and simulation components: iteration 1
D5.7 Security software modules: Iteration 1
D5.9 System architecture model and simulation platform: iteration 1
D6.1 Metrics Definition
D7.10 Update to the exploitation plan: iteration 1
D7.1 Visual identity, project website and social network account
D7.2 Update to the dissemination and communication plan: iteration 1
D7.6 Impact and Risk Assessment Report
NEUROPULS Project presentation A3 Poster
NEUROPULS Project presentation A5 Flyer
NEUROPULS Use cases A0 Scientific Poster
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